Modern integrated circuits (ICs) and the devices therein are at risk of damage due to electrostatic discharge (ESD) events. This is well known in the art. Accordingly, it is commonplace to provide an ESD clamp (voltage limiting device) across the input and/or other terminals of such devices and IC's. FIG. 1 is a simplified schematic diagram of circuit 20 wherein ESD clamp 21 is placed, for example, between input-output (I/O) terminal 22 and ground or common terminal 23 of an IC to protect other devices on the chip, that is, to protect “circuit core” 24 also coupled to I/O and common terminals 22, 23. Person of skill in the art will understand that ESD clamp 21 may be placed across any terminals of the IC or other device or circuit, and reference herein to I/O terminals is intended to include any and all other terminals not merely those used for input or output signals. Further, the Zener diode illustrated in block 21 of FIG. 1 is merely for convenience of identifying the voltage limiting function of ESD block 21 and not intended to imply that a Zener diode is present therein.
FIG. 2 is a simplified schematic diagram illustrating internal components of ESD clamp 21 utilizing bipolar transistor 25, having emitter 26, collector 27, base 28, and internal resistance 29. When the voltage across terminals 22, 23 rises beyond a predetermined limit, bipolar transistor 25 turns on, limiting the voltage across terminals 22, 23, desirably to a level below that capable of damaging circuit core 24.
FIG. 3 shows simplified plot 30 of transmission line pulse current (I) versus voltage (V) for a typical electrostatic discharge (ESD) protection device such as, for example, the device of FIG. 2. As the applied voltage is increased, very little current flows until triggering voltage 31 is reached at voltage Vt1. Once triggered into operation, the ESD device conducts and the current increases to holding point 32 with current Ih and voltage Vh. Depending upon the internal impedance of the voltage source, current and voltage may further increase to point 33 at current It2 and voltage Vt2, beyond which destructive failure may occur leading to further current increase accompanied by voltage decrease.
Electrostatic discharge (ESD) protection devices are intended to remain quiescent during normal operation of the associated semiconductor (SC) device(s) or non-SC device(s) or integrated circuit (IC) (i.e., the protected element(s) of circuit core 24) having a normal operating voltage Vo, but turn on when excessive voltage arises, thereby preventing damage to the protected element(s). The triggering voltage Vt1 of the ESD device should exceed the maximum normal DC operating voltage Vo(MAX) of the protected elements, otherwise the ESD device will interfere with normal operation of the protected elements. Further, Vt1 should be less than, for example, a voltage VTR (usually a transient voltage) large enough to damage the protected element(s), hereafter referred to as the protected element break-down voltage, abbreviated as VTR(PEBD). Thus, the ESD device should be designed so that Vo(MAX)<Vt1<VTR(PEBD).